Module definition of above instance is not found in the design verilog

In Verilog, modules are connected using module ports. For large modules, this is not productive as it involves Manually connecting hundreds of ports may lead to errors. Detailed knowledge of all the port is required. Difficult to change if the design changes. More time consuming. Most port declaration work is duplicated in many modules. Let us ... For Verilog linking, the Verilog files (.v files) for all modules in the design should be specified. Since most Verilog simulators will search in the path for any missing modules, you can often just specify one Verilog file. However, if the name or the location of a Verilog file is not obvious, you should give it explicitly on the command-line.